EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
Semiconductor Engineering

Easing Heterogeneous Cache Coherent SoC Design Using Arteris’ Ncore Interconnect IP

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and ...