Design-Reuse

Modelsim and gate verilog IP Listing

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ... The ...
Design-Reuse

Pentek Adds Pulse Compression IP Core to GateFlow Library for Xilinx Virtex FPGAs

Integrated Core Provides FPGA Alternative to DSPs in Radar Applications Flexible Design Offers 24 Variations to Match System Needs Optimized for Maximum Throughput or Minimum Resource Utilization ...