Design-Reuse

Software synthesis for embedded systems

Synthetic operating systems might mean never having to port software again. Software can be automatically generated-synthesized-to meet the demands of a changing system. For decades hardware design ...
EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...
Electronic Design

Q&A with Verific’s Rob Dekker on Parsers, Elaborators

Technology Editor Bill Wong talks with Rob Dekker about EDA, synthesis, parsers, and elaborators and why focusing on core competency is a recipe for success. Rob Dekker is CTO and Founder of Verific ...
Linux Journal

Xilinx FPGA Design Tools for Linux

A field programmable gate array (FPGA) is a user-programmable piece of silicon constructed in very large-scale integration (VLSI) technology. The VLSI transistor-level detail is absolutely predefined ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 1

With the advent of advanced HDLs – such as SystemVerilog – that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level ...