While the trend to use more and more design intellectual property (IP) has considerably reduced design effort per gate, it has had the exact inverse effect on the functional verification effort. In ...

It was probably no surprise to anyone when the idea of reuse first started to appear in the development of chips. At first the industry turned to salvaging, or the reuse of blocks that were never ...

Verification and validation of IP has gone well beyond simple simulation leaving the industry scrambling for new solutions amid growing problems. At the Design Automation Conference this year, the ...

Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for ...

The new Mentor EZ-VIP PCI Express Verification IP from Mentor Graphics Corp. reduces testbench assembly time for ASIC (application-specific integrated circuit) and FPGA (field-programmable gate array) ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and ...

Concentrating on transaction-based acceleration and in-circuit emulation use models, Cadence Design Systems reportedly has expanded its system verification IP and Cadence SpeedBridge Adapters ...

New Native System Verilog Ethernet VIP Complements Synopsys' 112G High-Speed SerDes PHY IP to Enable High-Performance Cloud Computing Solutions MOUNTAIN VIEW, Calif., March 23, 2020 /PRNewswire/ -- ...

MOUNTAIN VIEW, Calif., May 1, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first verification IP (VIP) for Non-Volatile Dual In-line Memory ...